1. Field of the Invention
The present invention relates to a display device and a method of driving the same. The present invention relates particularly to an active matrix type display device having a thin film transistor (referred to as a TFT hereinafter) formed on an insulator, and a method of driving the same, more particularly to an active matrix type display device using digital signals as picture signals, and a method of driving the same.
2. Related Art
In recent years, display devices having elements formed using a semiconductor thin film on an insulator, particularly on a glass substrate, have been spreading. For example, active matrix type display devices using a TFT have been spreading. In an active matrix display device, pixels are arranged in a matrix form and TFTs are arranged onto the respective pixels (the TFTs being referred to as pixel TFTs hereinafter). The pixel TFTs are used to control the brightness of the respective pixels, thereby displaying images.
Recently, there has been developing a technique of using a polycrystal semiconductor to form not only pixel TFTs constituting pixels but also TFTs constituting a driving circuit at the same time. This technique contributes greatly to miniaturization and low power consumption of display devices. Following this, an active matrix type display device has been becoming essential for the display section of portable information-processing equipment, the applicable field of which has been markedly expanding in recent years, or the like section. Examples of the active matrix type display device include an active matrix liquid crystal display device using a liquid crystal element, and an active matrix type organic light emitting diode (OLED) display device using an OLED element. In the present specification, attention is paid mainly to the active matrix type liquid crystal display device.
The above-mentioned liquid crystal element is composed of two electrodes, oriented films formed on the respective electrodes, and a liquid crystal material sandwiched between faces of the two electrodes on which the respective oriented films are formed. As the liquid crystal material, any material having a known structure can be used.
FIG. 6 schematically illustrates a conventional active matrix type liquid crystal display device of a system in which digital picture signals are used to perform display (referred to as a digital system here in after). At the center thereof, a pixel section 1308 is arranged.
In the pixel section 1308, plural pixels are arranged in a matrix form. Plural source signal lines and plural gate signal lines for inputting signals into the respective pixels are arranged.
A source signal line driving circuit 1301 for controlling signals to be inputted into the source signal lines is arranged over the pixel section 1308.
The source signal line driving circuit 1301 has a shift register 1303, the first latch circuit 1304, the second latch circuit 1305, D/A (digital/analogue) converter circuit 1306, which is illustrated as DAC in FIG. 6, an analogue switch 1307, and so on. Gate signal line driving circuits 1302 for controlling signals to be inputted to gate signal lines are arranged at the right and left sides of the pixel section 1308. Only one gate signal line driving circuit 1302 may be arranged at one side of the pixel section 1308. However, the case in which the gate signal line driving circuits are arranged at both the sides of the pixel section 1308 is more preferred from the viewpoints of driving efficiency and driving reliability.
The source signal line driving circuit 1301 has a configuration as illustrated in FIG. 7. The source signal line driving circuit, the example of which is illustrated in FIG. 7, is a source signal line driving circuit corresponding to a display device which has pixels, the number of which is x in the horizontal direction, so as to display gradation by the input of 3-bit digital picture signals (the gradation being referred to as 3-bit digital gradation).
The source signal line driving circuit illustrated in FIG. 7 has a shift register circuit (SR) 1401, the first latch circuit (LAT1) 1402, the second latch circuit (LAT2) 1403, D/A converter circuit (DAC) 1404, and so on. In FIG. 7, the analogue switch 1307 illustrated in FIG. 6 is not illustrated. If necessary, a buffer circuit, a level shift circuit, and so on, which are not illustrated in FIG. 7, may be arranged.
Referring to FIGS. 6 and 7, the following will describe the operation of the display device. First, clock signals (clock pulses, inverting clock pulses) and a start pulse are inputted to the shift register 1303, which are represented by xe2x80x9cSRxe2x80x9d in FIG. 7. As a result, pulses are successively inputted from the shift register circuit 1303 to the first latch circuit 1304, which are represented by xe2x80x9cLAT1xe2x80x9d in FIG. 7, so as to hold digital picture signals (digital data) which are similarly inputted to the first latch circuit 1304.
The most significant bit (MSB) of the digital picture signals is represented by D3, and the least significant bit (LSB) of the digital picture signals is represented by D1. After the holding of the digital data corresponding to one horizontal term is completed in the first latch circuit 1304, during a retrace line period the digital picture signals held in the first latch circuit 1304 are simultaneously transferred to the second latch circuit 1305, which is represented by xe2x80x9cLAT2xe2x80x9d in FIG. 7, by the input of a latch signal (latch pulse).
Thereafter, the shift register circuit 1303 is again operated to start the holding of digital data corresponding to the next horizontal term. At the same time, the digital data held in the second latch circuit 1305 are converted to analogue signals in the D/A converter circuit 1306, which is represented by xe2x80x9cDACxe2x80x9d in FIG. 7. The analogue signals are inputted to the source signal lines, represented by xe2x80x9cS1xe2x80x9d to xe2x80x9cSxxe2x80x9d in FIG. 7, and written in the respective pixels.
FIG. 8 illustrates a configuration of the pixel section of an ordinary active matrix type liquid crystal display device.
In each of pixels, a condenser 1001, a switching TFT 1002, and a liquid crystal element 1003 are arranged. The gate electrode of the switching TFT 1002 in each of the pixels is connected to some line of the gate signal lines G1 to Gy. One of the source region and the drain region of the switching TFT 1002 in each of the pixels is connected to some line of the source signal lines S1 to Sx, and the other is connected to either electrode of the condenser 1001 and either electrode of the liquid crystal element 1003.
The analogue signals inputted to the source signal lines S1 to Sx are inputted to the condensers 1001 and the liquid crystal elements 1003 across the drain and the source of the switching TFTs 1002 which have become conductive by the signals inputted to the gate signal lines G1 to Gy. Depending on the voltages of the signals, the transmittivity of the liquid crystal elements 1003 varies so that the brightness of the respective pixels is represented.
When an electric field along a given direction is constantly applied between the two electrodes of the liquid crystal element, ions in the liquid crystal material are prejudiced, thereby resulting in a problem that the liquid crystal element deteriorates. Thus, in display devices or the like wherein the ordinary liquid crystal element is used, there is used a driving method of changing, at regular intervals, the polarity of the voltage applied to the liquid crystal element so as to change the direction of the electric field applied to the two electrodes of the liquid crystal element.
For example, the following driving methods are known: a driving method called gate line inversion, a driving method called source line inversion, and a driving method called frame inversion.
In the driving method called gate line inversion, the polarities of signal voltages applied to liquid crystal elements are made different between gate signal lines adjacent to each other. In the driving method called source line inversion, the polarities of signal voltages applied to liquid crystal elements are made different between source signal lines adjacent to each other. In the driving method called frame inversion, the polarity of the signal voltage applied to the liquid crystal is inverted in every period when an image corresponding to one frame is displayed (the period being referred to as a frame period hereinafter).
Referring to timing charts shown in FIGS. 8 and 9, the following will describe the operation of this conventional active matrix type liquid crystal display device.
About the timing chart shown in FIG. 9, an operation based on the frame inversion driving is used.
Signals having a polarity contrary to signals inputted to the source signal line in the first frame period (F1) are inputted from the source signal line in the second frame period (F2). In the third frame period (F3), signals having a polarity different from that of the signals inputted in the second frame period (F2) are inputted.
In the first frame period (F1), the gate signal line G1 is firstly selected. As a result thereof, the switching TFT 1002 whose gate electrode is connected to the gate signal line G1 conducts. Thereafter, signals are inputted through the source signal lines S1 to Sx.
In the timing chart of FIG. 9, attention is paid to a certain source signal line Sm (m is a natural number of x or less) and only signals inputted to this source signal line Sm are shown. The period during which one gate signal line is selected is referred to as one horizontal term (one line period: L). Particularly, the period during which the gate signal line G1 is selected is referred to as the first line period L1.
After the input of a signal to the pixels having the switching TFTs 1002 connected to the gate signal line G1 finishes, a signal is inputted to the gate signal line G2 so that all of the switching TFTs 1002 connected to the gate signal line G2 conduct. In this way, the input of signals in the second line period L2 starts.
The above-mentioned operation is repeated about all of the gate signal lines G1 to Gy so that the repeated operation finishes in the yth line period Ly. As a result, one frame period ends.
Next, the second frame period (F2) starts. In the second frame period (F2), the polarity of signals inputted to the source signal line is different from the polarity of the signal voltage, of the source signal line, inputted to the source signal line in the first frame period (F1). In this way, images are displayed.
After the second frame period (F2) finishes, the third frame period (F3) starts. In the third frame period (F3), signal voltage having a polarity different from that of the signal voltage in the second frame period (F2) is inputted to the source signal line. In other words, signal voltage having the same polarity as in the first frame period is inputted to the source signal line.
The above-mentioned operation is repeated to display images.
In an ordinary active matrix type liquid crystal display device, display in its screen is renewed about 60 times per second in order to make the display of moving images smooth. In other words, it is necessary to supply digital picture signals in every frame period by the above-mentioned operation and perform writing in all of the pixels every time. Even if the picture to be displayed is a still image, the same signals must be continuously supplied in every frame period. It is therefore necessary that an external circuit, the driving circuit and so on continuously perform repetitive processing of the same digital picture signals.
There is also known a method of writing digital picture signals for a still image once in an external memory circuit and subsequently supplying the digital picture signals from the external memory circuit to a liquid crystal display device in every frame period. In either case, it is necessary that the external memory circuit and the driving circuit operate continuously.
Particularly in portable information-processing equipment, it is desired to make the power consumption thereof low. In portable information-processing equipment, the period during which a still image is continuously displayed occupies most of all periods. Notwithstanding this fact, the external circuit, the driving circuit and so on must operate continuously at the time when the still image is displayed, as described above. This fact prevents the power consumption from being made low.
Thus, an object of the present invention is to provide a liquid crystal display device making it possible to make the power consumption thereof low, and a method of driving the same.
The liquid crystal display device of the present invention comprises plural memory circuits for each pixel, and comprises one D/A converter circuit for each group of the plural pixels.
In the pixels having the above-mentioned structure, digital picture signals can be memorized in the plural memory circuits. The memorized digital picture signals can be converted to the corresponding analogue signals by the D/A converter circuit. The analogue signals make it possible to change the brightness of the respective pixels.
The following will describe the driving method of the display device of the present invention.
If data are once written in the respective pixels in the case of displaying a still image in the liquid crystal display device of the present invention, the same data are subsequently written in the pixels. Therefore, even if signals are not inputted in every frame period, the still image can be continuously displayed by reading out the signals memorized in the memory circuits again. That is, after signals corresponding to at least one frame period are subjected to processing-operation in order to display a still image, the external circuit, the source signal line driving circuit, and soon can be kept in a standstill state. In this way, the power consumption of the display device can be largely reduced.
The above is a basic description on the display device of the present invention and the method of driving the same.
The single D/A converter circuit is set up for each group of the plural pixels. Therefore, the D/A converter circuit is shared by the plural pixels.
In other words, one of the pixels sharing the D/A converter circuit is selected. Digital picture signals memorized in the selected pixel are inputted to the D/A converter circuit. In the D/A converter circuit, the inputted digital picture signals are converted to analogue signals. In this way, the brightness of the selected pixel is changed by the analogue signals.
The following will describe, for example, a case in which each pixel has a liquid crystal element.
One of the pixels sharing the D/A converter circuit is selected. Digital picture signals memorized in the selected pixel are inputted to the D/A converter circuit. In the D/A converter circuit, the inputted digital picture signals are converted to analogue signals. The analogue signals are inputted to the liquid crystal element which the selected pixel has. In this way, the brightness of the pixel is changed.
The following will describe the structure of the display device of the present invention.
In order to make the description simple, basic operation of the display device of the present invention will be firstly described about an example wherein no D/A converter circuit is shared, that is, an example wherein a D/A converter circuit is arranged for each pixel.
Plural memory circuits are arranged inside pixels, and digital picture signals are memorized in each of the pixels.
If data are once written in the pixels in the case of a still image, the same data are subsequently written in the pixels. Therefore, even if signals are not inputted in every frame period, the still image can be continuously displayed by reading out the signals memorized in the memory circuits again. That is, after signals corresponding to at least one frame period are subjected to processing-operation in order to display a still image, the external circuit, the source signal line driving circuit, and so on can be kept in a standstill state. In this way, the power consumption of the display device can be largely reduced.
This manner will be described.
Referring to the block view of FIG. 11, the following will describe a structural example of an active matrix type display device having the pixels comprising the above-mentioned memory circuits.
In FIG. 11, the display device is composed of a pixel section 1318, a source signal line driving circuit 1311, a gate signal line driving circuit 1312, and a DAC (D/A converter circuit) controller 1322.
A start pulse, clock pulses, digital data and latch pulses are inputted to the source signal line driving circuit 1311. A start pulse and clock pulses are inputted to the gate signal line driving circuit 1312. A reference voltage is inputted to the DAC controller 1322.
The source signal line driving circuit 1311 is paid attention to and will be described in detail. The source signal line driving circuit 1311 is composed of a shift register 1313, the first latch circuit 1314, the second latch circuit 1315 and switch 1317.
The source signal line driving circuit 1311 has a structure as illustrated in FIG. 12. The source signal line driving circuit, the example of which is illustrated in FIG. 12, is a source signal line driving circuit corresponding to a display device which has pixels, the number of which is x in the horizontal direction, so as to display gradation by the input of 3-bit digital picture signals (the gradation being referred to as 3-bit digital gradation).
This source signal line driving circuit has a shift register circuit (SR) 201, the first latch circuit (LAT1) 202, the second latch circuit (LAT2) 203, switch 204, and soon. If necessary, a buffer circuit, a level shift circuit, and so on, which are not illustrated in FIG. 12, may be arranged.
Referring to FIGS. 11 and 12, the following will describe the operation of the source signal line driving circuit. First, clock signals (clock pulses, inverting clock pulses) and a start pulse are inputted to the shift register 1313, which are represented by xe2x80x9cSRxe2x80x9d in FIG. 12. As a result, pulses are successively inputted from the shift register circuit 1313 to the first latch circuit 1314, which are represented by xe2x80x9cLAT1xe2x80x9d in FIG. 12, so as to hold digital picture signals (digital data) which are similarly inputted to the first latch circuit 1314. The pulses inputted from the shift register circuit 1313 to the first latch circuit 1314 are referred to as sampling pulses hereinafter.
The most significant bit (MSB) of the digital picture signals is represented by D3, and the least significant bit (LSB) of the digital picture signals is represented by D1. After the holding of the digital data corresponding to one horizontal term is completed in the first latch circuit 1314, during a retrace line period the digital picture signals held in the first latch circuit 1314 are simultaneously transferred to the second latch circuit 1315, which is represented by xe2x80x9cLAT2xe2x80x9d in FIG. 12, by the input of a latch signal (latch pulse).
Thereafter, the shift register circuit 1313 is again operated to start the holding of digital data corresponding to the next horizontal term. At the same time, the digital data held in the second latch circuit 1315 are selected, correspondingly to the respective bits, by bit selecting signals through the switch 1317, which is represented by xe2x80x9cSWxe2x80x9d in FIG. 12. The data are inputted to the source signal lines, represented by xe2x80x9cS1xe2x80x9d to xe2x80x9cSxxe2x80x9d in FIG. 12, and are then written in the respective pixels.
FIG. 10 illustrates a circuit configuration of the pixel to which signals are inputted from FIG. 12 in detail. The pixel corresponds to 3-bit digital gradation, and has a liquid crystal (LC), a retaining capacitor (capacitor element: Cs), memory circuits (M: 105-107), a D/A converter circuit (DAC: 111), and so on. Reference number 101 represents a source signal line; reference numbers 102-104, writing gate signal lines; and reference numbers 108-110, writing TFTs. The source signal line 101 corresponds to any one of the source signal lines S1 to Sx in FIG. 12.
In this device, the pixels, the number of which is x along the horizontal direction and is y along the vertical direction, are arranged in a matrix form. Three writing gate signal lines of the pixels in the first line are represented by 102-L1, 103-L1 and 104-L1. Three writing gate signal lines of the pixels in the yth line are represented by 102-Ly, 103-Ly and 104-Ly. Three writing TFTs of the pixels in the first line are represented by 108-L1, 109-L1 and 110-L1. Three writing TFTs of the pixels in the yth line are represented by 108-Ly, 109-Ly and 110-Ly.
FIG. 13 is a timing chart showing the method of driving the liquid crystal display device illustrated in FIGS. 10, 11 and 12. Referring to FIGS. 10-13, the driving method will be described.
In the source signal line driving circuit, digital picture signals are held in accordance with sampling pulses outputted from the shift register circuit 201 (digital data sampling).
Thereafter, a latch pulse is inputted during a retrace line period, so that the digital picture signal (digital data) transferred to the second latch circuit 203 are inputted to the source signal lines S1 to Sx.
One horizontal term can be classified into three periods, that is, the first bit writing period, the second bit writing period and the third bit writing period.
Through the switch 204, a bit selecting signal is inputted, so that the signal of the digital data D3 is inputted to the source signal lines S1 to Sx during the first bit writing period. At this time, the signal is inputted to the writing gate signal line 102-L1 so that the writing TFT 108-L1 connected to this writing gate signal line 102-L1 conducts. In this way, the signal D3 of the first bit is written in the memory circuit (M) 105.
Next, through the switch 204, a bit selecting signal is inputted during the second bit writing period, so that the signal of the digital data D2 is inputted to the source signal lines S1 to Sx. At this time, the signal is inputted to the writing gate signal line 103-L1 so that the writing TFT 109-L1 connected to this writing gate signal line 103-L1 conducts. In this way, the signal D2 of the second bit is written in the memory circuit (M) 106.
Next, through the switch 204, a bit selecting signal is inputted in the third bit writing period, so that the signal of the digital data D1 is inputted to the source signal lines S1 to Sx. At this time, the signal is inputted to the writing gate signal line 103-L1 so that the writing TFT 109-L1 connected to this writing gate signal line 103-L1 conducts. In this way, the signal D1 of the third bit is written in the memory circuit (M) 107.
In the above-mentioned way, the processing of the digital picture signals corresponding to one horizontal term finishes.
In the retrace line period of the third bit writing period, the digital picture signals written in the memory circuits (M) 105-107 are converted to analogue signals by the DAC 111. The period during which this digital/analogue conversion is performed is referred to as a DAC processing period. The analogue signals are inputted to the liquid crystal element LC and condenser (capacitor) Cs. Correspondingly to the analogue signals, the transmittivity of the liquid crystal element LC changes to represent gradation. Since the 3-bit digital picture signals are used, the brightness having 8 steps from 0 to 7 can be obtained.
By performing the above-mentioned operation for all lines of the pixels, an image corresponding to one frame is memorized in the respective pixels. The image is displayed.
The above-mentioned operation is repeated to display pictures continuously.
After digital picture signals are once memorized in the memory circuits 105-107 of the respective pixels by the first operation in the case of displaying a still image, it is advisable that the digital picture signals memorized in the memory circuits 105-107 are repeatedly read out by the DAC controller 1322 in respective frame periods. Therefore, during the period when this still image is displayed, the operation of the source signal line driving circuit can be stopped.
The above has described an example of the display device having three memory circuits in each pixel and having a function of memorizing 3-bit digital picture signals corresponding to one frame. However, the number of the memory circuits is not limited. That is, in order to memorize n-bit digital picture signals, wherein n is a natural number of 2 or more, corresponding to m frames, wherein m is a natural number, the number of memory circuits should be nxc3x97m per pixel.
By the above-mentioned method using the memory circuits arranged in the pixels, digital picture signals are memorized. When a still image is displayed, the digital picture signals memorized in the memory circuits are repeatedly used in respective frame periods. In this way, the still image can be continuously displayed without driving the external circuit, the source signal line driving circuit nor the like. Thus, the power consumption of the liquid crystal display device can be greatly reduced.
The above description is about the basis of the present invention.
In the case that the memory circuit and the D/A converter circuit (DAC) are arranged for each pixel, the element constituting the DAC occupies a large part of the pixel. Therefore, a problem that the area of the memory circuit inside the pixel is limited remains. Thus, it is difficult that the bit number for memorization per pixel is increased.
Consequently, it is difficult that the information amount of inputted digital signals is made large to realize high gradation and signals corresponding to many frame periods are memorized.
Therefore, in order to provide a liquid crystal display device which has a memory circuit for each pixel and a function of converting digital signals to analogue signals in its pixel section and further has a small area ratio of a D/A converter circuit in each pixel, each group of the plural pixels shares one D/A converter circuit.
The liquid crystal display device of the present invention is characterized in that a memory circuit is arranged in each pixel and each group of the plural pixels shares a D/A converter circuit. In this way, there can be provided a liquid crystal display device making it possible to arrange memory circuits corresponding to many bit numbers, and a method of driving the same.
The following will describe a structure of the liquid crystal display device of the present invention.
The present invention provides:
a liquid crystal display device for displaying a picture by inputting n-bit digital picture signals wherein n is a natural number of 2 or more, comprising a pixel section having plural pixels,
each of the pixels comprising memory circuits, the number of which is nxc3x97m wherein m is a natural number, a condenser, and a liquid crystal,
the pixels being divided into blocks, the number of the pixels in each of the blocks being k which is a natural number of 2 (inclusive) to n (inclusive), and
each of the blocks comprising a D/A converter circuit.
The present invention provides:
a liquid crystal display device for displaying a picture by inputting n-bit digital picture signals wherein n is a natural number of 2 or more, comprising a source signal line driving circuit, a gate signal line driving circuit, a DAC controller, and a pixel section,
the pixel section comprising plural pixels,
each of the pixels comprising memory circuits, the number of which is nxc3x97m wherein m is a natural number, a condenser, and a liquid crystal,
digital picture signals corresponding to at most m frames being memorized,
the pixels being divided into blocks, the number of the pixels in each of the blocks being k which is a natural number of 2 or more, and
each of the blocks comprising a D/A converter circuit.
The present invention provides a method of driving a liquid crystal display device, in which the n-bit digital picture signals memorized in one pixel i out of the k pixels are inputted to the D/A converter circuit of each of the blocks so as to convert the digital signals to analogue signals, and the analogue signals are inputted to the condenser and the liquid crystal element which the pixel i has.
The present invention provides a method of driving a liquid crystal display device, in which the n-bit digital picture signals memorized in one pixel i out of the k pixels are inputted to the D/A converter circuit of each of the blocks so as to convert the digital signals to analogue signals, and the operation of inputting the analogue signals to the condenser and the liquid crystal element which the pixel i has is continuously performed for all of the k pixels included in each of the blocks.
The present invention provides a method of driving a liquid crystal display device, in which in a period for displaying a still image, the operation of the source signal line driving circuit is stopped by repetitively reading out the n-bit digital picture signals memorized in the memory circuits by means of the DAC controller so as to display the still image.
The present invention provides a method of driving a liquid crystal display device, in which in a period for displaying a still image, the operation of the gate signal line driving circuit is stopped by repetitively reading out the n-bit digital picture signals memorized in the memory circuits by means of the DAC controller so as to display the still image.
The present invention provides a method of driving a liquid crystal display device, in which in a period for displaying a still image, the operation of the source signal line driving circuit and the operation of the gate signal line driving circuit are stopped by repetitively reading out the n-bit digital picture signals memorized in the memory circuits by means of the DAC controller so as to display the still image.
The present invention provides a method of driving a liquid crystal display device,
wherein the source signal line driving circuit comprises a shift register, a first latch circuit, a second latch circuit and a switch,
sampling pulses are outputted by a start pulse, a clock pulse, and an inversion clock pulse inputted to the shift register,
n-bit digital picture signals are held in the first latch circuit by the sampling pulses,
the n-bit digital picture signals held in the first latch circuit are transferred to the second latch circuit by a latch pulse,
the n-bit digital picture signals transferred to the second latch circuit are outputted through the switch to source signal lines, and
the n-bit digital picture signals outputted to the source signal lines are memorized in the memory circuits.
The present invention provides a method of driving a liquid crystal display device, in which the source signal line driving circuit successively inputs the n-bit digital picture signals, bit by bit, to the memory circuits.
The present invention provides a method of driving a liquid crystal display device, in which the source signal line driving circuit comprises an x-address decoder, and
in the memory circuits, data can be selectively written on individual vertical lines.
The present invention provides a method of driving a liquid crystal display device, in which the gate signal line driving circuit comprises a y-address decoder, and
in the memory circuits, data can be selectively written on individual horizontal lines.
The present invention provides a method of driving a liquid crystal display device, in which the source signal line driving circuit comprises an x-address decoder,
the gate signal line driving circuit comprises a y-address decoder, and
in the memory circuits, data can be selectively written in individual pixels having arbitrary coordinates.
The present invention may be a liquid crystal display device in which the pixels, the source signal line driving circuit, the gate signal line driving circuit, and the DAC controller are formed on a single substrate.
The present invention may be a liquid crystal display device in which the memory circuits are static random access memories (SRAM).
The present invention may be a liquid crystal display device in which the memory circuits are ferroelectric random access memories (FRAM).
The present invention may be a liquid crystal display device in which the memory circuits are dynamic random access memories (DRAM).
The present invention also provides a television, a personal computer, a portable terminal, a video camera, or a head mount display wherein a liquid crystal display device of the present invention is used.